1. Field of the Invention
The invention relates generally to the configurations and methods of manufacturing semiconductor power devices. More particularly, this invention relates to a device configuration and method of manufacturing a high voltage PiN (P-type/intrinsic/N-type) diode with low injection efficiency for improving the switching speed.
2. Description of the Prior Art
PiN diodes formed with conventional structures are still limited by a high modulation due to limited options for controlling the amount of anode and cathode electric charges injected as carriers into the intrinsic (or lowly doped) semiconductor layer typically disposed between the more heavily doped N-type and P-type layers. The difficulties cause the diode device to have a slow switching speed. Furthermore, the limited control of the charges also causes high reverse current and recovery time, which results in higher power consumptions and low operation efficiency.
A popular method of reducing the modulation is to employ carrier lifetime control techniques such as electron irradiation (ER), or gold and platinum diffusion to form deep level recombination sites. But these techniques require extra processing steps that add to the cost, and also cause increased leakage at high cathode biases. Furthermore, changes on the lifetime with temperature cause the diode reverse recovery to degrade significantly at high temperatures for lifetime controlled devices.
FIG. 1A is a cross sectional view of a conventional PiN diode (e.g. formed as a metal oxide semiconductor field effect transistor (MOSFET) body diode). The PiN diode includes an N buffer region 3 for soft recovery supported on a heavily doped N+ bottom substrate layer 4 nears the bottom surface. A lightly doped N− type (or intrinsic) layer 2 (e.g., an epitaxial layer) is formed on top of the N buffer layer 3 for blocking the voltage and a topside P layer 1 is formed (e.g., together with the implantation of a P-body region elsewhere on the die for a MOSFET) on top of the N− epitaxial layer 2. The lightly doped N-type layer 2 is the “intrinsic” portion of the PiN diode. By way of example, topside P-type layer 1 may have a doping concentration of about 1 E17/cm3 and a thickness of about 2 μm, the N-type epitaxial layer 2 may have a doping concentration of 1 E14/cm3 and a thickness of about 40 μm, the N-type buffer layer 3 may have a doping concentration of about 1 E15/cm3 and a thickness of about 10 μm, and the N-type bottom substrate layer 4 may have a doping concentration of about 1 E19/cm3, and a thickness of about 100 μm.
This high voltage PiN diode has a problem of high modulation which causes high switching losses and low switching speeds. The high modulation means high carrier injection and high stored charges. A large amount of carriers (e.g. P type charges) are injected from the topside P layer 1 into the N-type epitaxial layer 2, where they become stored charges. There is also charge injection from the heavily doped N type substrate 4 into the N type buffer region 3 and the lightly doped N type layer 2. This improves the forward conductivity of the diode, but leads to high switching losses and slow switching speed because those stored charges need to removed from the lightly doped layer 2 when the diode turns off.
In order to overcome this high modulation and slow switching of the PiN diode for high frequency applications, the topside P surface doping concentration is reduced as shown in FIG. 1B. The PiN diode of FIG. 1B has the same layer structures as FIG. 1A except that the topside P layer 1′ of FIG. 1B has a lower dopant concentration, e.g., 1 E16/cm3, in contrast to a dopant concentration of 1 E17/cm3 for topside P layer 1 of FIG. 1A. However, the lowering of topside P doping concentration is limited by punch through constraints. There needs to be enough P charge present to bring the electric field down to zero or else the device will punch through and leak heavily. Due to the punch through design consideration, the lowest surface P charge that is practical may be about Qp=2 E12/cm2. FIG. 1C shows another step to improve the device performance by lowering the N charge injection from the bottom side by back grinding away the N+ substrate 4 on the bottom side followed by carrying out a backside heavily doped N-type implant and anneal to form thin heavily doped N type back region 5 for making a good ohmic contact to the back side of the diode. Due to the ohmic contact constraint, the reduction of the N charge carriers in N type back region 5 has a lower limit of about Qn=5E12/cm2. Thus despite these steps, there are still limitations in the improvement of the device switching speed.
For all these reasons, there are great and urgent demands to improve the configurations and method of manufacturing the PiN diodes with improved control of charge injection and softness operation such that the above-discussed technical limitations and difficulties can be resolved.